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The Parallel Graph Reduction Machine, ALICE

Peter G. Harrison, Mike Reeve

Conference or Workshop Paper
Proceedings of a Workshop on Graph Reduction
October, 1986
Lecture Notes in Computer Science
Volume 279
DOI 10.1007/3-540-18420-1_55

Traditionally the design of programming languages has been compromised in order to exploit the most efficient machine architecture available, which has usually been of the von Neumann type. However, we believe that functional languages provide the most effective means for producing software and that the right approach is to develop a customised architecture for the implementation of the most suitable computational model for these languages.

In this paper we adopt graph reduction as the most natural computational model for functional languages and show how to represent it in a packet-based abstract computer architecture, ALICE. This architecture is highly parallel in nature, with a collection of processing agents performing redex reductions concurrently and asynchronously on the one hand, and the packets that represent the nodes in a function expression graph being distributed over several memory segments on the other. We suggest how a concrete parallel machine can be built to realise this abstract architecture, and describe the design of an experimental prototype machine. This prototype is a hardware emulator of the ideal concrete architecture which is to be built in customised VLSI, and is constructed using the INMOS Transputer as the basic building block. The design utilised a performance model to assist in choosing the optimal organisation of machine components, such as the ratio of processor to memory boards, and the model's predictions for the performance of various configurations of the machine are presented, along with some preliminary measurements made on the prototype. Finally, we make some suggestions for future design enhancements based on our experiences to date.

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