E Fiksman, Y Birk, Oskar Mencer
A Stream Compiler (ASC) generates netlists for hardware (FPGA) accelerators from C-like descriptions, obviating the need for hardware skills. We present a backend adapter that enables integration of such accelerators with a processor core in the same FPGA. Development of hybrid ASC-accelerated applications using software-only skills is thus made possible, as illustrated by a hybrid power-conscious iDCT implementation.
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