We present a new analytical performance model of the IEEE P1596 Standard Coherent Interface operating on the default unidirectional ring architecture. The performance metrics are derived from the equilibrium probability of a cache line being in a given state; these are found by solving a set of fixed point equations. From this we derive expressions for the message traffic emanating from each node and over the ring taking into account the relevant traffic priorities in SCI. Further analysis then yields the mean memory access time and processor utilisation. We demonstrate the application of the model by comparing the performance of two different node configurations.
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