Computing Publications

Publications Home » Domain-Specific FPGA: Architectur...

Domain-Specific FPGA: Architecture and Floating Point Applications

Chun Ho, Chi Wai Yu, Philip Leong, Wayne Luk, Steve Wilton

Conference or Workshop Paper
International Conference on Field Programmable Logic and Applications (FPL)
September, 2007
pp.196–201
Abstract

This paper presents a novel architecture for domain-specific FPGA devices. This architecture can be optimised for both speed and density by exploiting domain-specific information to produce efficient reconfigurable logic with multiple granularity. In the reconfigurable logic, general-purpose fine-grained units are used for implementing control logic and bit-oriented operations, while domain-specific coarse-grained units and heterogeneous blocks are used for implementing datapaths; the precise amount of each type of resources can be customised to suit specific application domains. Issues and challenges associated with the design flow and the architecture modelling are addressed. Examples of the proposed architecture for speeding up floating point applications are illustrated. Current results indicate that the proposed architecture can achieve 2.5 times improvement in speed and 18 times reduction in area on average, when compared with traditional FPGA devices on selected floating point benchmark circuits.

BibTEX file for the publication
 

pubs.doc.ic.ac.uk: built & maintained by Ashok Argent-Katwala.