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Optimizing Logarithmic Arithmetic on FPGAs

Haohuan Fu, Oskar Mencer, Wayne Luk

Conference or Workshop Paper
IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)
2007
pp.163–172
DOI 10.1109/FCCM.2007.50
Abstract

This paper proposes optimizations of the methods and

parameters used in both mathematical approximation and

hardware design for logarithmic number system (LNS)

arithmetic. First, we introduce a general polynomial approximation

approach with an adaptive divide-in-halves

segmentation method for evaluation of LNS arithmetic

functions. Second, we develop a library generator that automatically

generates optimized LNS arithmetic units with

a wide bit-width range from 21 to 64 bits, to support LNS

application development and design exploration. The basic

arithmetic units are tested on practical FPGA boards

as well as software simulation. When compared with existing

LNS designs, our generated units provide in most cases

6% to 37% reduction in area and 20% to 50% reduction

in latency. The key challenge for LNS remains on the application

level. We show the performance of LNS versus

floating-point for realistic applications: digital sine/cosine

waveform generator, matrix multiplication and radiative

Monte Carlo simulation. Our infrastructure for fast prototyping

LNS FPGA applications allows us to efficiently

study LNS number representation and its tradeoffs in speed

and size when compared with floating-point designs.

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