We present a new analytical performance model of the IEEE P1596 Standard Coherent Interface, which is a distributed cache coherency protocol for shared memory multiprocessors. We focus upon an implementation of the protocol on a unidirectional ring architecture (the default architecture for SCI systems). We identify the possible memory and cache line states and corresponding processor actions for a memory access and derive the equilibrium line state probabilities by solving a Markov model expressed as a set of fixed point equations. The probabilities of a processor performing a particular action then follow, from which the message transmission profile for each processor is derived. These traffic equations are then fed into an M/G/1 model for the ring architecture in which the ring traffic at a node has priority over traffic originating in that node. Further analysis then leads to the mean message transmission time, and hence the mean memory access time, and processor utilisation. We illustrate the application of the model by undertaking a performance comparison of two alternative node architectures and report some numerical results for various parameterisations.
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